Publications

Conferences

B. Bosquet, V. Brea, M. Mucientes. “Correlation-based ConvNet for Small Object Detection in Videos,” International Conference on Pattern Recognition (ICPR) 2020, Milán (Italia), Jan. 2021.

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G. Haessig, D. García-Lesta, G. Lenz, R. Benosman, P. Dudek, "A mixed-signal spatio-temporal signal classifier for on-sensor spike sorting," IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla (España), Oct. 2020.

DOI link:

https://doi.org/10.1109/ISCAS45731.2020.9180442

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D. García-Lesta, P. López, V. Brea, D. Cabello. “CMOS Vision Sensor for Background Subtraction”. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla (España), Oct. 2020.

DOI link:

https://doi.org/10.1109/ISCAS45731.2020.9180735

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Ó. Pereira-Rial, P. López, Juan M. Carrillo, V.M. Brea, D. Cabello. “1.88 nA Quiescent Current Capacitor-Less LDO with Adaptive Biasing Based on a SSF Absolute Voltage Difference Meter”. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla (España), Oct. 2020.

DOI link:

https://doi.org/10.1109/ISCAS45731.2020.9181143

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D. Cores, M. Mucientes, V. Brea. “RoI Feature Propagation for Video Object Detection,” European Conference on Artificial Intelligence, pp. 8. Santiago de Compostela (España), Sept. 2020.

DOI link:

https://doi.org/10.3233/FAIA200406

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Ó. Pereira-Rial, Juan M. Carrillo, P. López, V.M. Brea, D. Cabello. “Design methodology of a 0.7 V, 64.5 pW @ 36°C, 1830 μm² Subthreshold Voltage Reference for Implantable Devices,” 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Génova (Italia), Nov. 2019.

DOI link:

https://doi.org/10.1109/ICECS46596.2019.8964763

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A. Muñío-Gracia, J. Fernández-Berni, R. Carmona-Galán, Á. Rodríguez-Vázquez, “VersaTile Convolutional Neural Network Mapping on FPGAs,” IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, October 2020.

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J.A. Díaz-Madrid, G. Doménech-Asensi, R. Ruiz-Merino, J. Zapata-Pérez, J.J. Martínez-Álvarez, “Mixed signal multiply and adder parallel circuit for deep learning convolution operations”, IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, May 2020.

DOI link:

https://doi.org/10.1109/ISCAS45731.2020.9180757

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G. Doménech-Asensi, T.J. Kazmierski, "High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors", Design, Automation and Test in Europe Conference (DATE), Grenoble, France, March 2020.

DOI link:

http://www.doi.org/10.23919/DATE48585.2020.9116270

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G. Doménech-Asensi and T. J. Kazmierski, "Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors," Forum for Specification and Design Languages (FDL), Southampton, United Kingdom, 2019

DOI link:

https://doi.org/10.1109/FDL.2019.8876903

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